1. Field of the Invention
The present invention relates generally to the field of reflective array display devices, and, more particularly, to a novel reflective array structure that provides a novel multi-mirror structure for maximizing aperture ratio while minimizing optical power absorption.
2. Discussion of the Prior Art
In transmissive or reflection display arrays, it is desirable to have the aperture ratio of the cell as high as possible to minimize the amount of illumination required and optical power absorption by the array. A better display results from higher brightness and efficiency.
FIG. 1 illustrates the physical layout of an absorbing gap cell 10, e.g., 10 .mu.m pitch, for a LCD reflection display light valve with FIG. 2 illustrating its equivalent circuit. As shown in FIG. 2, in an active matrix array LCD display, each pixel "cell" comprises a (thin-film) transistor 15, and a capacitance 20, and other components (not shown) and, may be fabricated using well-known CMOS fabrication techniques.
With more particularity, as shown in FIGS. 1 and 2, the absorbing gap cell 10 includes the following important functional layers: a conductive "P1" layer (doped polysilicon) providing a control signal to the gate of the transistor 20 row for determining the optical properties of the cell and forming one electrode of capacitor "C.sub.sub " and having another electrode return via the substrate; a first metal layer "M1" for carrying data signals to the source terminal of the active transistor 15; a top-surface aluminum mirror layer "M2" located beneath the liquid crystal material (not shown) and forming one electrode of the liquid crystal display capacitor element C.sub.LC and having a top plate electrode formed of a transparent conductor such as ITO. Additionally, as part of the fabrication of the absorbing gap cell design, there is an anti-reflecting "AR" layer which forms a capacitance C.sub.AR with the M2 and M1 metal layers.
FIG. 3(a) illustrates a cross-sectional view of the absorbing gap cell 10 of FIG. 1 taken along line X1-X1'. FIG. 3(b) illustrates a cross-sectional view of the absorbing gap cell 10 of FIG. 1 taken along line Y1-Y1'. As shown in FIGS. 3(a) and 3(b), the cell includes: regions of implanted Silicon, for example, N.sup.+ regions, indicated as region "RX" and forming the gate and drain/source regions for the thin-film transistor 20;
the P1 poly-Si conductive layer forming a gate for the transistor and one electrode of capacitance C.sub.sub with the other electrode formed of the implanted Si (RX layer); the first metallization layer M1 for carrying data control signals to the source terminal of the active transistor layer RX and providing another end of capacitor C.sub.AR ; the second metallization layer which is an light energy absorber layer "AR", e.g., formed of a tri-layer composite of titanium-nitride, aluminum, and titanium; and, the third level metallization layer M2 which is a top-surface aluminum mirror layer located beneath the liquid crystal material (not shown) and providing the liquid crystal cell with reflective optical properties. As shown in FIG. 1 and FIG. 3(a), a contact "CA" is provided for connecting the M1 layer to the P1 contact.
As further shown in FIG. 3(b), the titanium-nitride, aluminum, titanium anti-reflective or absorbing layer AR is provided between the M1 and M2 layers throughout the cell. The anti-reflective or light absorption is provided by the top titanium nitride layer, with the aluminum core layer providing the conductivity and the titanium underlayer providing the good contact and a barrier between the aluminum and the underlying SiO.sub.2. This AR layer is held at the top plate electrode potential (connection not shown) and, typically is fabricated at a depth below the M2 mirror surface that is equal to an integer number of .lambda./(2*n) for polarized illumination oriented in the normally black mode where .lambda. is the wavelength of the illuminating light. The aluminum mirror M2 is shown contacting the M1 metal layer underneath the AR absorbing layer by the provision of via "V1", which may be a tungsten plug, for example, connecting M1 and M2 layers. As shown in FIG. 1 and 3(a), a region AR of the AR layer is removed about the via V1 so as to electrically isolate the AR layer.
In an active matrix array comprising absorbing gap pixel cells (of c-Si technology) shown in FIG. 1, the M2 reflecting mirror surface area covers a fraction of the pixel surface area with exposed gaps "G" remaining within the cell. Disposed underlying the gaps "G" is the AR layer between the mirrors M1 and M2 that absorbs illumination energy. Thus, if the illumination directed at the cell is of high enough intensity, then optical power absorbed and heat removal from the array may be a design problem because the light valve array is typically packaged for compactness and accommodating heat sink sizes may expand the packaging, and/or require additional fan cooling which adds system weight and noise. This additionally applies to absorbing gap cells fabricated of p-Si technology which utilize a glass substrate (not shown). These problems are compounded in reducing cell pitch or incorporating binary area weighted mirrors. Thus, the prior art absorbing gap cell design exhibits a decreased aperture ratio, i.e., decreased light reflection efficiency.
It is the case then that an increase in aperture ratio is very desirable as this would reduce the illumination requirements and reduce array power absorption, thereby saving cost.